1. Field of the Invention
The present invention relates to an echo canceller apparatus, more particularly to an echo canceller which corrects a receive clock and a transmit clock which are asynchronous with each other.
2. Description of the Related Art
As is disclosed, for example, in Japanese Patent Application Laid Open No. 7-202767, this kind of echo canceller apparatus has been used to absorb a slip between timings of receive and transmit systems and to cancel a near-end echo signal from a transmit input signal using a signal of a receive system as a reference signal, in a digital four-wire path in which clocks of the receive system and that of the transmit system are asynchronous.
FIG. 1 is a block diagram showing an example of a conventional echo cancller apparatus. The echo canceller apparatus consists of a memory of a FIFO style (hereinafter referred to as FIFO) 311; a delay device 312 for delaying an enable signal; an A/D converter 314 for performing a digital conversion for a transmit input signal; an echo canceller 315; a selection circuit 316; and a fixed data generator 317.
The FIFO 311 has a capability of writing digital receive data at a timing of its receive clock and reading it at a timing of its transmit clock. Moreover, an enable signal En and a delayed enable signal DEn which has been delayed by the delay device 312 by a predetermined sampling time are input to the FIFO 311. The FIFO 311 is reset by starting-up of the enable signal En to start a writing operation for the receive data and the FIFO 311 starts a reading operation for it by the starting-up of the delayed enable signal DEn.
The enable signal En is a control signal showing whether the receive data is effective or ineffective. For example, a voice level detection is conducted on the transmit side to decide whether voice is effective or ineffective.
The delayed enable signal DEn which has been delayed by a predetermined sampling period by the delay device 312 is input to the selection circuit 316. The selection circuit 316 selects one of the outputs from the FIFO 311 and the fixed data generator 317 based on the delay enable signal DEn.
The fixed data generator 317 is a circuit which generates direct current data at a control signal level. The D/A converter 313 performs an analog conversion for the output selected by the selection circuit 316 and transmits it as a received output. The A/D converter 314 performs a digital conversion for a transmit input signal at a transmit timing and outputs it to an echo canceller 315.
The echo canceller 315 receives the output from the selection circuit 316 as a reference signal. Therefore, the echo canceller 315 receives the receive data as a reference signal, the receive data being read out from the FIFO 311 at a transmit timing. The echo canceller 315 removes an echo component from the digital transmit data output from the A/D converter 314 and transmits the transmit data.
Next, an operation of the foregoing echo canceller apparatus will be described. First, when the enable signal En is at a voice ineffective period, the delayed enable signal DEn is also at the voice ineffective period. Therefore, the selection circuit 316 selects the direct current data which are output from the fixed data generator 317 and outputs it to the D/A converter 313. Then, when the enable signal En enters the voice effective period, the FIFO 311 is initialized in synchronization with the starting-up of the enable signal En and the receive data is written to the FIFO 311 according to the receive timing.
On the other hand, when the delayed enable signal DEn enters the voice effective period, the FIFO 311 performs reading-out of the receive data, which had previously been according to the transmit data timing in parallel with the writing operation of the receive data. The reading operation of the receive data is continuously performed during the voice effective period of the delay enable signal DEn.
The receive data which is read out according to the timing of the transmit clocks as described above is converted to an analog signal by the A/D converter 313 and is transmitted. Also, the echo canceller 315 removes the echo component from the transmit data using this receive data as a reference signal.
Subsequently, when the delayed enable signal DEn enters the voice ineffective period, the selection circuit 316 switches the selection from the FIFO 311 to the fixed data generator 317 again to stop the output from the FIFO 311 and outputs the direct current data output from the fixed data generator 317 to the D/A converter 313.
It is possible to absorb the slip between the writing timing of the receive data (receive timing) and the reading timing (transmit timing) for the FIFO 311 by controlling the writing and reading operations of the FIFO 311 using the enable and delayed enable signals En and DEn, even though both timings are asynchronous with each other.
In the foregoing prior arts, when it is decided that the receive input signal is at the voice effective period for a long time because background noises at a predetermined level or more are included in the receive input signal, a capacity limitation of the FIFO is exceeded. Therefore, since normal operations of the writing of the receive input signal by the timing of the receive clock and the reading of it by the timing of the transmit clock are not compensated, if the voice effective period of the receive input signal continues for a long time, the slip between the receive and transmit clocks is accumulated. As a result, it becomes impossible to absorb the timing slip which accumulated between them.
Moreover, by transiting from the voice effective period to the voice ineffective period, a variation in an apparent echo path is produced in the echo canceller. Therefore, the transition from the voice effective period to the voice ineffective period produces a data slip in the receive input signal, whereby an echo estimation operation of the echo canceller falls into disorder so that an echo is not canceled at a time.